A LOC (Lead-On-Chip) package is one kind of semiconductor packages by attaching the leads of a leadframe directly to the active surface of a chip without using die pads of a leadframe under the chip so that the length of the bonding wires from the bonding pads of the chip to the fingers of a leadframe can greatly be reduced leading to higher operation frequencies with lower packaging costs.
As shown in FIG. 1 and FIG. 2, a conventional semiconductor package 100 primarily comprises a chip 110, a plurality of first leads 120 and a plurality of second leads 150 of a leadframe, a plurality of bonding wires 141, 142, and 144. The chip 110 has an active surface 111 with a plurality of bonding pads 112 disposed in a single row on the active surface 111. The first leads 120 and the second leads 150 are extended from both corresponding sides of the semiconductor package 100 onto the active surface 111 of the chip 110. The first leads 120 and the second leads 150 are attached to the active surface 111 of the chip 110 by a die-attaching material 160 where the internal leads of the first leads 120 and the internal leads of the second leads 150 inside an encapsulant 170 include a plurality of first fingers 121 and the second fingers 151 for bonding the bonding wires 141 and 142, as shown in FIG. 2. The leadframe further has one or more bus bars 130 attached to the active surface 111 of the chip 110 disposed between the center bonding pads 112 and the fingers 121 of the first leads 120 or/and between the center bonding pads 112 and the fingers 151 of the second leads 150. Normally the bus bars 130 are configured for power or ground connections. As shown in FIG. 2, the bonding wires 141 and 142 have one ends bonded to the center bonding pads 112 of the chip 110 and overpass the bus bar 130 so that the other ends of the bonding wires 141 and 142 are bonded to the first fingers 121 of the first leads 120 and to the second fingers 151 of the second leads 150 respectively to make electrical connections between the chip 110 and the leadframe. At least one bonding wire 144 connects one pad 112A of the center bonding pads 112 to the bus bar 130, which has a shorter length than the one of the bonding wires 141 and 142. The encapsulant 170 encapsulates the chip 110, the internal leads of the leads 120 and 150, the bonding wires 141, 142, and 144. However, due to higher I/O density and miniature of a chip, arranging the center bonding pads in a row will be gradually replaced by multiple rows such as two rows of bonding pads.
Currently, chips with multiple rows of bonding pads packaging into LOC semiconductor packages have lower packaging yields due to different lengths of bonding wires from multiple rows of bonding pads to fingers at one side, especially the lengths of the bonding wires from a farther row of bonding pads overpassing the bus bar to the corresponding fingers become longer leading to lower yields resulting in difficulty in wire-bonding. Moreover, the longer bonding wires will suffer wire sweep during molding with electrical short to the bus bar leading to poor qualities of electrical connections.